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markos_hi, anyone knows of an asm instruction (or instructions) to find out the L1/L2 (well no ARM with L3 cache yet) cache sizes on ARM? Or some way to read it from the kernel?09:43
markos_similar to cpuid on recent x86 cpus09:45
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=== JaMa|Away is now known as JaMa
markos_lool: I'm about to give up, no matter what I do, wanna-build just fails to even produce the database, you did mention an alternative a while ago, a gsoc project, got any more info on that?16:16
ssvbmarkos_: the registers which can be used to get this information are described in ARM ARM, but they are not accessible from userspace16:23
ssvbmarkos_: kernel provides some of the cpu specific information via /proc/cpuinfo and /proc/self/auxv16:24
markos_ssvb: cpuinfo doesn't carry this info though, actually I thought of auxv, but it's not straightforward and I thought I'd ask first16:26
ssvbmarkos_: yes, this information may be incomplete, for example auxv did not even report NEON availability before linux kernel 2.6.2916:28
ssvbmarkos_: if you are really interested in having this information, pushing some patches to the kernel to get it may be useful16:29
ssvbmarkos_: btw, http://pastebin.com/3rvXx68s16:30
markos_hm, I guess it depends on the platform16:30
markos_what kernel version?16:30
markos_strange, I get none of the cache info here ( on the imx51516:31
ssvblooks like somebody is being lazy and is not keeping this code up to date :)16:31
loolmarkos_: pkern was working on a python-based wanna-build replacement16:32
markos_ssvb: still on x86 and ppc, L1/L2 cache info can be found on /sys/devices/system/cpu/cpu0/cache/index# etc16:32
markos_ssvb: would be nice to have it work the same on arm also16:33
markos_lool: anything published?16:33
loolmarkos_: google "Debian Autobuilding Infrastructure Rewrite"; I don't know how complete the rewrite ended up being16:34
loolmarkos_: Ping pkern or HE on #debian-devel@oftc?16:34
ssvbmarkos_: I have only 'cpufreq' there, but not 'cache', anyway it is clearly a problem on the kernel side, preferably it should provide this information in a consistent way16:35
ssvbmarkos_: alternatively it would be interesting if the kernel could just provide access to cpuid related registers (or emulate their behavior)16:36
ssvbwhy do you need to know cache size?16:37
markos_eigen library does block size configuration -or is able to do so- by matching matrix blocks according to the L1/L2/L3 cache sizes, it gets some extra % speed that way -at least on x8616:38
markos_there's cpuid on x86 which gives that info -amongst others16:39
ssvba somewhat ugly solution would be to run a small benchmark to get this information in an experimental way16:41
markos_that's too error prone16:41
ssvbiirc, fftw does something like this16:41
ssvbright, but in the worst case it will just impact performance, nothing else16:42
markos_which is the point behind all this :)16:42
ssvbare you going to bug kernel developers about providing this information?16:44
markos_if it's possible, I can use it, if not, well, eigen is only a linear algebra library, running mini benchmarks at startup isn't going to be accepted by the authors anyway16:44
markos_ssvb: I might, time permitting16:45
markos_tbh, I've never filed a bug report on the kernel before, but there's always a first time :)16:45
markos_the info is already available anyway16:46
markos_first I have to setup this this autobuilder setup16:46
markos_lool: I guess soyuz cannot be installed standalone...16:50
loolmarkos_: No, but we're working exactly on that19:25
loolmarkos_: Actually, according to the soyuz devs it's not that hard to run it standalone19:25
loolmarkos_: What you will miss is the Launchpad API19:26
looland obviously the web UI19:26
loolmarkos_: I'm not sure where the work related to splitting soyuz out is tracked; it should be in a blueprint but I'm not sure where19:26
loolmarkos_: Ideally, ping james_w if you want to follow these discussions19:28

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